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general description the MAX11902 is an 18-bit, 1msps, single-channel, fully differential sar adc with internal reference buffers. the MAX11902 provides excellent static and dynamic perfor - mance with best-in-class power consumption that directly scales with throughput. the device has a unipolar differ - ential v ref input range. supplies include a 3.3v supply for the reference buffers, a 1.8v analog supply, a 1.8v digital supply, and a 1.5v to 3.6v digital interface supply. this adc achieves 98.9db snr and -123db thd, guar - antees 18-bit resolution with no-missing codes and 1.5 lsb inl (max). the MAX11902 communicates data using a spi- compatible serial interface. the MAX11902 is offered in a 20-pin, 4mm x 4mm, tqfn package and is specified over the -40c to +85c* operating temperature range. applications test and measurement automatic test equipment medical instrumentation process control and industrial automation data acquisition systems telecommunications battery-powered equipment benefts and features high dc/ac accuracy provides better measurement quality ? 18-bit resolution with no missing codes ? 1.5 lsb inl and 0.5 lsb dnl maximum at 18 bits ? 98.9db snr and 98.8db sinad at f in = 10khz ? -125db sfdr and -123db thd at f in = 10khz high sampling rate sar architecture enables fast settling and acquisition ? 1msps throughput with no pipeline delay integration simplifies design ? integrated reference buffers ? v ref unipolar differential analog input range scalable ultra-low power supply reduces power consumption ? 6.7mw at 1msps ? scale as 6.7w/ksps flexible low-voltage supplies save cost ? 1.8v analog and digital core supply ? 1.5v to 3.6v digital interface supply ? 3.3v refvdd reference buffer supply flexible, industry-standard serial interface and small package reduce size ? spi-/qspi?-/microwire ? /dsp-compatible ? 20-pin, 4mm x 4mm, tqfn package ordering information and selector guide appears at end of data sheet. qspi is a trademark of motorola, inc. microwire is a registered trademark of national semiconductor corporation. 16-bit to 20-bit sar adc family 1 nf cog max 11902 cnvst dout sclk din avdd dvdd ovdd refin refvdd ain + ain - 4 - wire spi interface 3 . 3 v 3 . 6 v 1 . 8 v 1 . 8 v 1 . 5 to 3 . 6 v 7 . 5 ? 7 . 5 ? 3 . 3 v to 0 v 0 to 3 . 3 v refgnd ref dgnd agnd 10 f 3 . 3 v 16-bit 18-bit 20-bit 1.6m sps max11901 max11903 max11905 1m sps max11900* MAX11902 max11904* *for extended operation temperature, contact maxim. *future product 19-7170; rev 0; 9/14 application diagram evaluation kit available MAX11902 18-bit, 1msps, low-power, fully differential sar adc
maxim integrated 2 table of contents general description ............................................................................ 1 applications .................................................................................. 1 features and benefits .......................................................................... 1 application diagram ............................................................................ 1 16-bit to 20-bit sar adc family ................................................................. 1 absolute maximum ratings ...................................................................... 4 package thermal characteristics ................................................................. 4 electrical characteristics ........................................................................ 4 typical operating characteristics ................................................................. 8 pin configuration ............................................................................. 12 pin description ............................................................................... 12 functional diagram ........................................................................... 13 detailed description ........................................................................... 14 analog inputs .............................................................................. 14 input settling ............................................................................... 16 input filtering .............................................................................. 16 voltage reference configurations .............................................................. 17 transfer function ........................................................................... 17 digital interface .............................................................................. 19 spi timing diagram ......................................................................... 20 register write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 register read .............................................................................. 22 register map ................................................................................ 23 mode register .............................................................................. 23 conversion result register ................................................................... 24 chip id register ............................................................................ 24 typical application circuit ...................................................................... 24 single-ended unipolar input to differential unipolar output .......................................... 24 single-ended bipolar input to differential unipolar output ........................................... 24 layout, grounding, and bypassing ............................................................... 24 definitions ................................................................................... 27 integral nonlinearity ....................................................................... 27 differential nonlinearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 offset error ............................................................................. 27 gain error ............................................................................... 27 signal-to-noise ratio ...................................................................... 27 signal-to-noise plus distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 www.maximintegrated.com MAX11902 18-bit, 1msps, low-power, fully differential sar adc
maxim integrated 3 table of contents ( continued ) list of figures list of tables figure 1. signal ranges ........................................................................ 14 figure 2. simplified model of input sampling circuit .................................................. 15 figure 3. conversion frame, sar conversion, track and read operation ................................ 15 figure 4. ideal transfer characteristic ............................................................ 18 figure 5. read during track phase ............................................................... 19 figure 6. read during sar conversion phase ...................................................... 19 figure 7. split read mode ...................................................................... 20 figure 8. spi interface connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 9. din timing for register write operations .................................................. 21 figure 10. timing diagram for data out reading after conversion ...................................... 21 figure 11. mode register write .................................................................. 22 figure 12. register read ....................................................................... 22 figure 13. unipolar single-ended input ............................................................ 25 figure 14. bipolar single-ended input ............................................................. 25 figure 15. top layer sample layout .............................................................. 26 table 1. adc driver amplifier recommendation ..................................................... 16 table 2. voltage reference configurations ......................................................... 17 table 3. MAX11902 external reference recommendations ............................................ 17 table 4. transfer characteristic .................................................................. 18 table 5. dout driver strength .................................................................. 23 effective number of bits ................................................................... 27 total harmonic distortion .................................................................. 27 spurious-free dynamic range .............................................................. 27 aperture delay ........................................................................... 27 aperture jitter ........................................................................... 27 full-power bandwidth ..................................................................... 27 selector guide ............................................................................... 28 ordering information .......................................................................... 28 chip information .............................................................................. 28 package information .......................................................................... 28 revision history .............................................................................. 29 www.maximintegrated.com MAX11902 18-bit, 1msps, low-power, fully differential sar adc
refvdd, ref, refin, ovdd to gnd .................. -0.3v to +4v avdd, dvdd to gnd ............................................. -0.3v to +2v dgnd to agnd, refgnd .................................. -0.3v to +0.3v ain+, ain- to gnd ...... -0.3v to the lower of (v ref + 0.3v) and +4v or 130ma sclk, din, dout, cnvst, to gnd ........... -0.3v to the lower of (v ovdd + 0.3v) and +4v maximum current into any pin ........................................... 50ma continuous power dissipation (t a = +70c) tqfn (derate 30.30mw/c above +70c) ............. 2424.2mw operating temperature range ........................... -40c to +85c junction temperature ...................................................... +150c storage temperature range ............................ -65c to +150c lead temperature (soldering, 10s) ................................. +300c soldering temperature (reflow) ....................................... +260c tqfn junction-to-ambient thermal resistance ( ja ).... .. ....33c/w junction-to-case thermal resistance ( jc ) ....... ... ..... 2c/w (note 1) (f sample = 1msps, v avdd = 1.8v, v dvdd = 1.8v, v ovdd = 1.5v to 3.6v, v refvdd = 3.6v, v ref = 3.3v, internal ref buffers on, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) (note 2) parameter symbol conditions min typ max units analog input input voltage range (note 3) (ain+) - (ain-) -v ref +v ref v absolute input voltage range ain+, ain- relative to agnd -0.1 v ref + 0.1 v common-mode input range [(ain+) + (ain-)]/2 v ref /2 - 0.1 v ref /2 v ref /2 + 0.1 v input leakage current acquisition phase -1 0.001 +1 a input capacitance 32 pf static performance (note 4) resolution n 18 bits resolution lsb v ref = 3.3v 25.2 v no missing codes 18 bits offset error (note 4) -2.5 1 +2.5 lsb offset temperature coeffcient 0.004 lsb/c gain error referred to refin reference input -50 5 +50 lsb gain error temperature coeffcient (note 5) referred to refin reference input 0.05 lsb/c gain error referred to ref pins -12 4 +12 lsb gain error temperature coeffcient (note 5) referred to ref pins 0.04 lsb/c integral nonlinearity inl -1.5 0.5 +1.5 lsb maxim integrated 4 note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to ab solute maximum rating conditions for extended periods may affect device reliability. package thermal characteristics electrical characteristics www.maximintegrated.com MAX11902 18-bit, 1msps, low-power, fully differential sar adc
(f sample = 1msps, v avdd = 1.8v, v dvdd = 1.8v, v ovdd = 1.5v to 3.6v, v refvdd = 3.6v, v ref = 3.3v, internal ref buffers on, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) (note 2) parameter symbol conditions min typ max units differential nonlinearity (note 6) dnl -0.5 0.25 +0.5 lsb analog input cmr cmr dc 5 lsb/v power-supply rejection (note 7) psr psr vs. avdd 0.6 lsb/v power-supply rejection (note 7) psr psr vs. refvdd 1 lsb/v transition noise 0.99 lsb rms external reference ref voltage input range v ref 2.5 3.3 3.6 v load current i ref 1msps, v ref = 3.3v 350 a ref input capacitance 1 nf reference buffer refin input voltage range v refin v ref < (v refvdd - 200mv) 2.5 3 v refvdd - 200mv v refin input current i refin 1 na turn-on settling time c ext = 10f on ref pin, c refin = 0.1f on refin pin 20 ms external compensation capacitor c ext ref pins 4.7 10 f dynamic performance (note 8) dynamic range internal refbuffer, -60dbfs input 99.4 db signal-to-noise ratio snr internal refbuffer, f in = 10khz 97.7 98.9 db signal-to-noise plus distortion sinad internal refbuffer, f in = 10khz, -0.1dbfs 97.6 98.8 db spurious-free dynamic range sfdr internal refbuffer, f in = 10khz 125 db total harmonic distortion thd internal refbuffer, f in = 10khz -123 db total harmonic distortion thd internal refbuffer, f in = 100khz -115 db total harmonic distortion thd internal refbuffer, f in = 250khz -107 db sampling dynamics throughput 0 1 msps full-power bandwidth -3db point 20 mhz -0.1db point 3 acquisition time t acq 150 ns aperture delay time delay from cnvst rising edge to time at which sample is taken for conversion 1 ns aperture jitter 3 ps rms maxim integrated 5 electrical characteristics (continued) www.maximintegrated.com MAX11902 18-bit, 1msps, low-power, fully differential sar adc
(f sample = 1msps, v avdd = 1.8v, v dvdd = 1.8v, v ovdd = 1.5v to 3.6v, v refvdd = 3.6v, v ref = 3.3v, internal ref buffers on, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) (note 2) parameter symbol conditions min typ max units power supplies analog supply voltage avdd 1.7 1.8 1.9 v digital supply voltage dvdd 1.7 1.8 1.9 v reference buffer supply voltage refvdd 2.7 3.3 3.6 v interface supply voltage ovdd 1.5 3.6 v analog supply current i avdd v avdd = 1.8v 1.75 2.3 ma digital supply current i dvdd v dvdd = 1.8v 1.5 1.9 ma reference buffer supply current i refvdd v refvdd = 3.6v, internal buffers enabled 3.3 3.55 ma reference buffer supply current i refvdd v refvdd = 3.6v, internal buffers powered down 0.2 ma interface supply current (note 9) i ovdd v ovdd = 1.5v 0.27 ma v ovdd = 3.6v 1 shutdown current for avdd, dvdd, refvdd 1 a shutdown current for dvdd 1 a power dissipation v avdd = 1.8v, v dvdd = 1.8v, v refvdd = 3.3v, internal reference buffers disabled 6.7 8.4 mw digital inputs (din, sclk, cnvst) input voltage high v ih v ovdd = 1.5v to 3.6v 0.7 x v ovdd v input voltage low v il v ovdd = 1.5v to 3.6v 0.3 x v ovdd v input capacitance c in 10 pf input current i in v in = 0v or v ovdd 1 a digital outputs (dout) output voltage high v oh i source = 2ma v ovdd - 0.4 v output voltage low v ol i sink = 2ma 0.4 v maxim integrated 6 electrical characteristics (continued) www.maximintegrated.com MAX11902 18-bit, 1msps, low-power, fully differential sar adc
(f sample = 1msps, v avdd = 1.8v, v dvdd = 1.8v, v ovdd = 1.5v to 3.6v, v refvdd = 3.6v, v ref = 3.3v, internal ref buffers on, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) (note 2) note 2: limits are 100% production tested at t a = +25c. limits over the operating temperature range are guaranteed by design and device characterization. note 3: see the analog inputs section. note 4: see the definitions section at the end of the data sheet. note 5: see the definitions section at the end of the data sheet. error contribution from the external reference not included. note 6: parameter is guaranteed by design. note 7: defined as the change in positive full-scale code transition caused by a 5% variation in the supply voltage. note 8: sine wave input, f in = 10khz, a in = -0.1db below full scale. note 9: c load = 10pf on dout. f conv = 1msps. all data is read out. parameter symbol conditions min typ max units timing din to sclk rising edge setup t 1 4 ns din to sclk rising edge hold t 2 1 ns dout end-of-conversion low time t 3 15 ns dout to sclk rising edge hold t 4 2.5 ns dout to sclk rising edge setup t 5 100mhz sclk 1.5 ns sclk high t 6 4.5 ns sclk period t 7 10 ns sclk low t 8 4.5 ns cnvst rising edge to sclk rising edge t 9 0 ns sclk rising edge to cnvst rising edge t 10 25 ns cnvst high t 11 25 ns cnvst high to eoc t 12 850 ns conversion period t 13 1000 ns maxim integrated 7 electrical characteristics (continued) www.maximintegrated.com MAX11902 18-bit, 1msps, low-power, fully differential sar adc
(v avdd = 1.8v, v dvdd = 1.8v, v ovdd = 1.8v, v refvdd = 3.6v, f sample = 1msps, v ref = 3.3v, internal ref buffer on, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 dnl (lsb) temperature ( o c) dnl vs. temperature max dnl (lsb) min dnl (lsb) toc4 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.70 1.73 1.75 1.78 1.80 1.83 1.85 1.88 1.90 dnl (lsb) v avdd (v) dnl vs. avdd supply voltage max dnl (lsb) min dnl (lsb) v refvdd = 3.6v v ref = 3.3v toc6 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 inl (lsb) temperature ( o c) inl vs. temperature max inl (lsb) min inl (lsb) toc3 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.70 1.73 1.75 1.78 1.80 1.83 1.85 1.88 1.90 inl (lsb) v avdd (v) inl vs. avdd supply voltage max inl (lsb) min inl (lsb) v refvdd = 3.6v v ref = 3.3v toc5 toc1 maxim integrated 8 typical operating characteristics www.maximintegrated.com MAX11902 18-bit, 1msps, low-power, fully differential sar adc
(v avdd = 1.8v, v dvdd = 1.8v, v ovdd = 1.8v, v refvdd = 3.6v, f sample = 1msps, v ref = 3.3v, internal ref buffer on, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) -4 -2 0 2 4 -40 -25 -10 5 20 35 50 65 80 95 110 125 error (lsb) temperature ( c) offset (lsb) gain error (lsb) offset and gain error vs. temperature v ref = 3.3v v refvdd = 3.6v toc9 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 offset error (lsb) v refvdd (v) v ref = 2.5v v avdd = 1.8v offset error vs. refvdd voltage toc11 -4.0 -3.0 -2.0 -1.0 0.0 1.0 2.0 3.0 4.0 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 inl (lsb) v refvdd (v) inl vs. refvdd supply voltage max inl (lsb) min inl (lsb) v avdd = 1.8v v ref = 2.5v toc7 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 1.7 1.75 1.8 1.85 1.9 offset error (lsb) v avdd (v) v ref = 3.3v v refvdd = 3.6v offset error vs. avdd supply voltage toc10 0 10000 20000 30000 40000 50000 60000 131091 131092 131093 131094 131095 131096 131097 131098 131099 131100 number of occurrences output code (decimal) output noise histogram toc12 stdev = 0.99 lsb rms -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 dnl (lsb) v refvdd (v) dnl vs. refvdd supply voltage max dnl (lsb) min dnl (lsb) v avdd = 1.8v v ref = 2.5v toc8 maxim integrated 9 typical operating characteristics (continued) www.maximintegrated.com MAX11902 18-bit, 1msps, low-power, fully differential sar adc
(v avdd = 1.8v, v dvdd = 1.8v, v ovdd = 1.8v, v refvdd = 3.6v, f sample = 1msps, v ref = 3.3v, internal ref buffer on, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) 115 117 119 121 123 125 127 129 131 133 135 -40 -25 -10 5 20 35 50 65 80 95 110 125 sfdr and thd (db) temperature ( c) -thd sfdr sfdr and thd vs. temperature toc16 110 113 115 118 120 123 125 128 130 2.0 2.2 2.3 2.5 2.6 2.8 2.9 3.1 3.2 sfdr and thd (db) v ref (v) sfdr -thd thd and sfdr vs. reference voltage toc18 95 96 97 98 99 100 -40 -25 -10 5 20 35 50 65 80 95 110 125 snr and sinad (db) temperature ( c) snr sinad snr and sinad vs. temperature toc15 94 95 96 97 98 99 100 2 2.3 2.6 2.9 3.2 3.5 snr and sinad (db) v ref (v) sinad snr snr and sinad vs. reference voltage toc17 maxim integrated 10 typical operating characteristics (continued) www.maximintegrated.com MAX11902 18-bit, 1msps, low-power, fully differential sar adc
(v avdd = 1.8v, v dvdd = 1.8v, v ovdd = 1.8v, v refvdd = 3.6v, f sample = 1msps, v ref = 3.3v, internal ref buffer on, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) 0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.3 0.5 0.8 1.0 current (ma) sampling rate (msps) current vs. sampling rate idvdd iovdd iavdd toc21 0 5 10 15 20 25 30 -40 -25 -10 5 20 35 50 65 80 95 110 125 shutdown current (a) temperature ( c) iavdd iovdd irefvdd idvdd shutdown current vs. temperature toc20 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 -40 -25 -10 5 20 35 50 65 80 95 110 125 current (ma) temperature ( c) iovdd irefvdd (buffer off) irefvdd idvdd iavdd current vs. temperature toc19 maxim integrated 11 typical operating characteristics (continued) www.maximintegrated.com MAX11902 18-bit, 1msps, low-power, fully differential sar adc
pin name i/o function 1, 2 ref i/o reference. ref is a bypass pin for the reference either driven by the internal reference buffers or the external reference directly. bypass these pins with 10f capacitors to refgnd. 3, 4 refgnd i reference ground 5 ain- i negative analog input 6 ain+ i positive analog input 7 agnd i analog ground 8 ovdd i digital interface supply. nominally at 1.8v. bypass to dgnd with a 10f capacitor in parallel with a 0.1f capacitor (10f || 0.1f). 9 dout o digital output data 10 dgnd i digital ground 11 dvdd i digital supply. nominally at 1.8v. bypass with a 10f capacitor in parallel with a 0.1f capacitor (10f || 0.1f). 12 sclk i serial clock input 13 cnvst i conversion start. the analog inputs (ain+, ain-) are sampled at the rising edge and conversion process is started. 14 din i serial data input. din data is latched into the serial interface on the rising edge of sclk. 15 dgnd i digital ground ref ain - ref din sclk dvdd dgnd agnd avdd refin dout ovdd agnd ain + + refgnd cnvst agnd dgnd refvdd tqfn 4 mm 4 mm max 11902 top view refgnd 10 9 8 7 6 11 12 13 14 15 5 4 3 2 1 16 17 18 19 20 exposed pad is ground. it must be soldered to pcb. maxim integrated 12 pin description pin confguration www.maximintegrated.com MAX11902 18-bit, 1msps, low-power, fully differential sar adc
pin name i/o function 16 refvdd i reference buffer supply. nominally at 3v. bypass to agnd with a 10f capacitor in parallel with a 0.1f capacitor (10f || 100nf). 17, 18 agnd i analog ground. 19 avdd i analog supply. nominally at 1.8v. bypass to agnd with a 10f capacitor in parallel with a 0.1f capacitor (10f || 100nf). 20 refin i input for the internal reference buffer. voltage must be at least 200mv lower than refvdd voltage. if refin = 0v, reference buffer will be disabled. ep exposed pad. must be connected to the same plane as agnd. 18 - bit adc refvdd refgnd ref ref ain + ain - interface din sclk dout cnvst refin avdd dvdd agnd dgnd max 11902 ovdd reference buffer reference buffer maxim integrated 13 functional diagram pin description (continued) www.maximintegrated.com MAX11902 18-bit, 1msps, low-power, fully differential sar adc
detailed description the MAX11902 is an 18-bit, 1msps maximum sampling rate, fully differential input, single-channel sar adc with spi interface. this part features industry-leading sample rate and resolution, while consuming very low power. the MAX11902 has an integrated reference buffer to minimize board space, component count, and system cost. an internal oscillator drives the conversion and sets conver - sion time, easing external timing considerations. analog inputs both analog inputs, ain+ and ain-, range from 0v to v ref . thus, the differential input interval v diff = (ain+) - (ain-) ranges from -v ref to +v ref , and the full-scale range is: ref fsr 2 x v = the nominal resolution step width of the least significant bit (lsb) is: n fsr lsb ,n 18 2 = = the differential analog input must be centered around a signal common mode of v ref /2, with a tolerance of 100mv. the reference voltage can range from 2.5v to the refer - ence supply, refvdd, if an external reference buffer is used. when using the on-board reference buffer the reference voltage can range from 2.5v to 200mv below reference supply refvdd. this will guarantee adequate headroom for the internal reference buffers. figure 1 illustrates signal ranges for ain+/ain-, reference voltage v ref and reference supply voltage refvdd. figure 2 shows the input equivalent circuit of MAX11902. the adc samples both inputs, ain+ and ain-, with a fully differential on-chip track-and-hold exhibiting no pipeline delay or latency. the MAX11902 has dedicated input clamps to protect the inputs from overranging. diodes d1 and d2 provide esd protection and act as a clamp for the input voltages. diodes d1/d2 can sustain a maximum forward current of 100ma. the sampling switches connect inputs to the sampling capacitors. figure 3 shows the timing of the digitizing cycle: conversion frame, sar conversion, track and read operations. figure 1. signal ranges v ref 0v 0.5 x v ref ain+ ain- v ref v refvdd 3.6v if buffer is disabled v ref +200mv v refvdd 3.6v if buffer is enabled 200mv refvdd v time maxim integrated 14 www.maximintegrated.com MAX11902 18-bit, 1msps, low-power, fully differential sar adc
figure 3. conversion frame, sar conversion, track and read operation figure 2. simplified model of input sampling circuit r on = 260? ain+ refvdd c in = 30pf d1 d2 v dc r on = 260? ain- refvdd d1 d2 c in = 30pf cnvst sclk dout track read data sample 1 sar conversion 1 / sample rate sample 2 msb msb - 1 lsb + 1 lsb msb msb - 1 lsb + 1 lsb track read data sar conversion 1 / sample rate reading sample 1 during track reading sample 2 during track sample 1 sample 2 maxim integrated 15 www.maximintegrated.com MAX11902 18-bit, 1msps, low-power, fully differential sar adc
input settling during track phase ( figure 3 ), the sample switches are closed and the analog inputs are directly connected to the sample capacitors. the charging of the sample capacitor to the input voltage is determined by the source resis - tance and sampling capacitor size. the rising edge of cnvst is the sampling instant for the adc. at this instant, the track phase ends, the sample switch opens, and the device enters into the successive approximation (sar) conversion phase. in the conversion phase, a differential comparator compares the voltage on the sample capaci - tor against the cdac value, which cycles through values between v ref /2 and v ref /2 20 using the successive approximation technique. the final result can be read via the spi bus. the adc automatically goes back into track phase at the end of sar conversion and powers down its active circuits. that is, the adc consumes no static power in track mode. the conversion results will be accurate if the adc tracks the input signal for an interval longer than the input sig - nals settling time. if the signal cannot settle within the track time due to excessive source resistance, external adc drivers are required to achieve faster settling. since the MAX11902 has a fixed conversion time set by an internal oscillator, track time can be increased by lowering the sample rate for better settling. the settling behavior is determined by the time constant in the sampling network. the time constant depends upon the total resistance (source resistance + switch resis - tance) and total capacitance (sampling capacitor, external input capacitor, pcb parasitic capacitors). modeling the input circuit with a single pole network, the time constant, r total c load , of the input should not exceed t track /15, where r total is the total resistance (source resistance + switch resistance), c load is the total capacitance (sampling capacitor, external input capacitor, pcb parasitic capacitor), and t track is the track time. when an adc driver is used, it is recommended to use a series resistance (typically 5 to 50) between the amplifier and the adc input, as shown in the application diagram . below are some of the requirements for the adc driver amplifier: 1) fast settling time: for a multichannel multiplexed cir - cuit the adc driver amplifier must be able to settle with an error less than 0.5 lsb during the minimum track time when a full-scale step is applied. 2) low noise: it is important to ensure that the adc driver has a sufficiently low-noise density in the bandwidth of interest of the application. when the MAX11902 is used with its full bandwidth of 20mhz, it is preferable to use an amplifier with an output noise spectral den - sity of less than 3nv/ hz , to ensure that the overall snr is not degraded significantly. it is recommended to insert an external rc filter at the adc input to attenuate out-of-band input noise. 3) to take full advantage of the adcs excellent dynamic performance, maxim recommends the use of an adc driver with equal or even better thd performance. this will ensure that the adc driver does not limit distortion performance in the signal path. table 1 sum - marizes the most important features of the max9632 when used as an adc driver. input filtering noisy input signals should be filtered prior to the adc driver amplifier input with an appropriate filter to minimize noise. the rc network shown in the application diagram is mainly designed to reduce the load transient seen by the amplifier when the adc starts the track phase. this network also has to satisfy the settling time requirement and provides the benefit of limiting the noise bandwidth. table 1. adc driver amplifier recommendation amplifier input-noise density (nv/ hz ) small-signal bandwidth (mhz) slew rate (v/s) thd (db) i cc (ma) comments max9632 1 55 30 -128 3.9ma low noise, thd at 10khz maxim integrated 16 www.maximintegrated.com MAX11902 18-bit, 1msps, low-power, fully differential sar adc
voltage reference confgurations the MAX11902 features internal reference buffers, helping to reduce component count and board space. alternatively, the user may drive the reference nodes ref with an external reference. to use the internal reference buffers, drive the refin pin with an external reference voltage source. it will appear on the ref pin as a buffered reference output. the internal reference buffers can be disabled by writing to a register (see the mode register section) or tying refin to 0v. once the on-chip reference buffers are disabled, ref pins can be directly driven by external reference buffers. a simplified diagram is shown to clarify the required connections for external reference. a low-noise, low-temperature drift reference is required to achieve high system accuracy. the max6126 and max6325 are particularly well suited for use with the MAX11902. the max6126 and max6325 offer, respec - tively, 0.02% and 0.04% initial accuracy and 3ppm/c and 1ppm/c (max) temperature coefficient for high-precision applications. maxim recommends bypassing refin and ref with a 2.2f capacitor close to the adc pins. transfer function figure 4 shows the ideal transfer characteristics for the MAX11902. the default data format is twos complement. however, offset binary format can be chosen by setting mode regis - ter bit 1 (see the mode register section). table 4 shows the codes in terms of input voltage applied. the data reported is with v ref of 3.0v, that gives a full- scale range of 6v. table 3. MAX11902 external reference recommendations table 2. voltage reference configurations part v out (v) temperature coefficient (ppm/c, max) initial accuracy (%) noise (0.1hz to 10hz) (v p-p ) package max6126 2.5, 3 3 0.02 1.45 max-8, so-8 max6325 2.5 1 0.04 1.5 so-8 reference configuration internal reference buffers refin v ref v refvdd internal reference buffer on 2.5v to v refvdd - 0.2v 2.5v to v refvdd - 0.2v 2.7v to 3.6v external reference buffer off tie to 0v or disable through serial interface 2.5v to v refvdd 2.5v to 3.6v maxim integrated 17 www.maximintegrated.com MAX11902 18-bit, 1msps, low-power, fully differential sar adc
table 4. transfer characteristic figure 4. ideal transfer characteristic midcode value differential analog input full-scale range = 6v (v) hexadecimal twos complement hexadecimal offset binary fs - 1 lsb 2.99997711 0x1ffff 0x3ffff midscale + 1 lsb 0.00002289 0x00001 0x20001 midscale 0.00000000 0x00000 0x20000 midscale - 1 lsb -0.00002289 0x3ffff 0x1ffff -fs + 1 lsb -2.99997711 0x20001 0x00001 -fs -3.00000000 0x20000 0x00000 111...111 111...110 111...101 000...000 000...001 000...010 output code (offset binary) v in = (ain+) - (ain-) differential analog input (lsb) fs - 1.5 x lsb 2 x v ref full scale (fs) v in = +v ref zero scale (zs) v in = -v ref -2 17 -2 17 +1 -2 17 +2 2 17 2 17 -1 2 17 -2 011...111 011...110 011...101 100...000 100...001 100...010 output code (two's complement) v in = (ain+) - (ain-) differential analog input (lsb) fs - 1.5 x lsb -2 17 -2 17 +1 -2 17 +2 2 17 2 17 -1 2 17 -2 2 x v ref full scale (fs) v in = +v ref zero scale (zs) v in = -v ref maxim integrated 18 www.maximintegrated.com MAX11902 18-bit, 1msps, low-power, fully differential sar adc
digital interface the MAX11902 has a spi interface with cnvst control - ling the sampling, and sclk, dout, din forming the standard spi signals. the sar conversion begins with the rising edge of cnvst. the minimum cnvst high time is 20ns and cnvst should be brought low before dout goes low, which signals the completion of a sar conversion. the dout goes low for 15ns, followed by the output of the msb on the dout pin. the 18-bit con - version result can then be read via the spi interface by sending 18 sclk pulses. dout going low also signals the start of the track phase. the adc stays in track phase until the next rising edge of cnvst. the MAX11902 has three different modes to read the data: reading during track phase ( figure 5 ) reading during sar conversion phase ( figure 6 ) split reading ( figure 7 ) when reading during track phase mode, the data is read only while the adc is in track mode. figure 5 shows the spi signal for this reading mode. in the reading during sar conversion phase mode, the data is read only in the sar conversion phase. figure 6 illustrates all spi signals for this mode. note that the data being read only during the sar conversion phase corresponds to the previous conversion frame. figure 5. read during track phase figure 6. read during sar conversion phase cnvst sclk dout track read data sample 1 sar conversion 1 / sample rate sample 2 msb msb - 1 lsb + 1 lsb msb msb - 1 lsb + 1 lsb track read data sar conversion 1 / sample rate reading sample 1 during track reading sample 2 during track sample 1 sample 2 cnvst sclk track read data sample 1 sar conversion 1 /sample rate sample 2 msb dout msb-1 lsb +1 lsb msb msb -1 lsb +1 lsb track read data sar conversion 1 /sample rate reading sample 0 during sar conversion sample 1 sample 0 reading sample 1 during sar conversion msb maxim integrated 19 www.maximintegrated.com MAX11902 18-bit, 1msps, low-power, fully differential sar adc
in the split reading mode, the data is read during the track phase and the following sar conversion phase. figure 7 shows the descriptive timing diagram. at higher sampling rates, the track time may not be long enough to allow reading all 18 bits of data. in this case, the data read can be started in track mode, and then continued in the subsequent sar conversion phase. note that the read operation must be completed before dout goes low, signaling the end of the sar conversion phase. also note that no sclk pulses should be applied close to the sampling edge (rising edge of cnvst), to safeguard the sampling edge from digital noise (see the quiet time specification t 10 ). this split reading feature can be used to accommodate slower spi clocks. spi timing diagram figure 8 shows the typical digital spi interface connection between the MAX11902 and host processor. the dashed connections are optional. figure 9 shows the timing diagram for configuration reg - isters. figure 10 shows the timing diagram for data output read - ing after conversion. figure 7. split read mode figure 8. spi interface connection cnvst sclk dout track read data sample 1 sar conversion 1 / sample rate sample 2 msb msb - 1 lsb + 1 lsb msb msb - 1 track read data sar conversion 1 / sample rate quiet time reading sample 1 sample 1 sample 2 host processor cnvst dout sclk din max 11905 cnvst sclk dout din irq maxim integrated 20 www.maximintegrated.com MAX11902 18-bit, 1msps, low-power, fully differential sar adc
figure 10. timing diagram for data out reading after conversion figure 9. din timing for register write operations msb msb - 1 msb - 2 dout t 3 t 4 sclk t 12 t 5 0 . 7 x ovdd 0 . 3 x ovdd t 6 t 8 t 11 t 7 0 . 7 x ovdd 0 . 3 x ovdd 0 . 7 x ovdd 0 . 7 x ovdd t 10 t 9 0 . 7 x ovdd t 13 cnvst 0 . 7 x ovdd t 1 t 2 0 . 7 x ovdd sclk 0 . 3 x ovdd din maxim integrated 21 www.maximintegrated.com MAX11902 18-bit, 1msps, low-power, fully differential sar adc
register write all spi operations start with a command word. the structure of the command word is shown below. if there is no start bit, i.e. din is low, the part will output the conversion result and then go idle (see figures 5 , 6 , and 7 ). the 16-bit mode register is the only register that can be written to. figure 11 shows the waveform for a mode register write operation. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 start 0 adr 3 adr 2 adr 1 adr 0 r/w 0 register read a read operation is specified by setting the r/ w bit high. data will be output by the MAX11902 after the 8th rising sclk edge. figure 12 shows the waveform for a mode register read. figure 11. mode register write figure 12. register read cnvst sclk din dout 0 st a3 a2 a0 d15 d14 r/w 0 d1 d0 a1 cnvst sclk din dout 0 st a3 a2 a0 d7 d6 0 d1 d0 a1 r/w maxim integrated 22 www.maximintegrated.com MAX11902 18-bit, 1msps, low-power, fully differential sar adc
register map function address r/ w bits data width data read or write mode register 0001 1 or 0 16 mode register read conversion result* 0010 1 18 conversion result read chip id 0100 1 8 chip id reserved, do not use all other reserved, do not use *conversion result can also be read as shown in figures 5 , 6 , and 7 . mode register the reset state is: 0x0000. that is, the reference buffers are enabled if a valid reference voltage is applied at the refin pin. if external reference buffers are used, tie refin low and the buffers will be automatically powered down. dd[2:0] program the driver strength on dout pin. higher driver strengths are for systems that have larger capacitive loads on dout. the lowest driver strength that works should be chosen to save power and improve performance. the driver strength is ordered from 1 to 6. the driver strength 1 is the weakest while the driver strength 6 is the strongest. table 5 shows the mapping between the register value d[2:0] and the correspondent driver strength. table 5. dout driver strength bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset dd2 dd1 dd0 pd ref1 por pass otp busy ob pd ref2 reset: reset the part when high. dd[2:0]: program the driver strength on dout. pd ref1: power down the first reference buffer when set. por pass: high to indicate that por was successful. if this bit is low, reset should be asserted. otp busy: high to indicate that the device is powering up. ob: output data format is offset binary when high. twos complement when low. pd ref2: power down the second reference buffer when set. dd[2:0] driver strength 000 4 001 5 010 6 011 not valid 100 1 101 2 110 3 111 not valid maxim integrated 23 www.maximintegrated.com MAX11902 18-bit, 1msps, low-power, fully differential sar adc
conversion result register an 18-bit read-only register, can be read directly or via a command read sequence. chip id register this register holds a 4-bit code that can be used to verify the silicon revision. the id = 1001b. typical application circuit real-world signals usually require conditioning before they can be digitized by an adc. the following outlines common examples of analog signal processing circuits for shifting, gaining, attenuating, and filtering signals. single-ended unipolar input to differential unipolar output the circuit in figure 13 shows how a single-ended, uni - polar signal can interface with the MAX11902. this signal conditioning circuit transforms a 0v to +v ref single-end - ed input signal to a fully differential output signal with a signal peak-to-peak amplitude of 2 x v ref and common- mode voltage (v ref /2). in this case, the single-ended signal source drives the high-impedance input of the first amplifier. this amplifier drives the ain+ input of adc and the second stage amplifier with peak-to-peak amplitude of v ref and common-mode output voltage of v ref /2. the second amplifier inverts this input signal and adds an offset to generate an inverted signal with peak-to-peak amplitude of v ref and common-mode output voltage of v ref /2, which drives the ain- input of adc. single-ended bipolar input to differential unipolar output the MAX11902 is a differential input adc that accepts a differential input signal with unipolar common mode. figure 14 shows a signal conditioning circuit that trans - forms a -2 x v ref to +2 x v ref single-ended bipolar input signal to a fully differential output signal with ampli - tude peak-to-peak 2 x v ref and common-mode voltage v ref /2. the single-ended bipolar input signal drives the inverting input of the first amplifier. this amplifier inverts and adds an offset to the input signal. it also drives the ain- input of adc and the second stage amplifier with peak-to-peak amplitude of v ref and common-mode output voltage of v ref /2. the second amplifier is also in inverting configu - ration and drives the ain+ input of the adc. this ampli - fier adds an offset to generate a signal with peak-to-peak amplitude of v ref and common-mode output voltage of v ref /2. the input impedance, seen by the signal source, depends on the input resistor of the first-stage inverting amplifier. input impedance must be chosen care - fully based on the output source impedance of the signal source. layout, grounding, and bypassing for best performance, use pcbs with ground planes. ensure that digital and analog signal lines are separated from each other. do not run analog and digital lines paral - lel to one another (especially clock lines), and avoid run - ning digital lines underneath the adc package. a single solid gnd plane configuration with digital signals routed from one direction and analog signals from the other pro - vides the best performance. connect the gnd pin on the MAX11902 to this ground plane. keep the ground return to the power supply for this ground low impedance and as short as possible for noise-free operation. a 2nf c0g ceramic chip capacitor should be placed between ain+ and ain- as close as possible to the MAX11902. this capacitor reduces the voltage transient seen by the input source circuit. for best performance, connect the ref output to the ground plane with a 16v, 10f ceramic chip capacitor with a x5r dielectric in a 1210 or smaller case size. ensure that all bypass capacitors are connected directly into the ground plane with an independent via. bypass avdd, dvdd, and ovdd to the ground plane with 10f ceramic chip capacitors on each pin as close as pos - sible to the device to minimize parasitic inductance. for best performance, bring the avdd and dvdd power plane in from the analog interface side of the MAX11902 and the ovdd power plane from the digital interface side of the device. figure 15 shows the top layer of a sample layout. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 id3 id2 id1 id0 maxim integrated 24 www.maximintegrated.com MAX11902 18-bit, 1msps, low-power, fully differential sar adc
figure 13. unipolar single-ended input figure 14. bipolar single-ended input v ref 0v 0.5 x v ref r + - r s r s c s cog MAX11902 cnvst dout sclk din avdd dvdd ovdd refin refvdd ain+ ain- dsp spi interface 2.5v to v refvdd - 0.2v 2.7v to 3.6v 1.8v 1.8v 1.5v to 3.6v r refgnd ref dgnd agnd 10f v ref 2 r + - r s r s c s cog MAX11902 cnvst dout sclk din avdd dvdd ovdd refin refvdd ain+ ain- dsp spi interface 2.5v to v refvdd - 0.2v 2.7v to 3.6v 1.8v 1.8v 1.5v to 3.6v r +2 x v ref 0v r 4r r + - 4r -2 x v ref v ref 2 v ref 2 refgnd ref dgnd agnd 10f maxim integrated 25 www.maximintegrated.com MAX11902 18-bit, 1msps, low-power, fully differential sar adc
figure 15. top layer sample layout maxim integrated 26 www.maximintegrated.com MAX11902 18-bit, 1msps, low-power, fully differential sar adc
defnitions integral nonlinearity integral nonlinearity (inl) is the deviation of the values on an actual transfer function from a straight line. for these devices, this straight line is a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. differential nonlinearity differential nonlinearity (dnl) is the difference between an actual step width and the ideal value of 1 lsb. for these devices, the dnl of each digital output code is measured and the worst-case value is reported in the electrical characteristics table. a dnl error specification of less than 1 lsb guarantees no missing codes. offset error the offset error is defined as the deviation between the actual output and ideal output measured with 0v differen - tial analog input voltage. gain error gain error is defined as the difference between the actual output range measured and the ideal output range expected. it is measured with signal applied at the input with an amplitude close to full-scale range. signal-to-noise ratio for a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (snr) is the ratio of the full- scale analog input power to the rms quantization error (residual error). the ideal, theoretical minimum analog- to-digital noise is caused by quantization noise error only and results directly from the adcs resolution (n bits): snr = (6.02 x n + 1.76)db in reality, there are other noise sources besides quantiza - tion noise: thermal noise, reference noise, clock jitter, etc. snr is computed by taking the ratio of the signal power to the noise power, which includes all spectral components not including the fundamental, the first five harmonics, and the dc offset. signal-to-noise plus distortion signal-to-noise plus distortion (sinad) is the ratio of the fundamental input frequencys power to the power of all the other adc output signals: signal sinad(db) 10 log noise distortion ?? = ?? + ?? effective number of bits the effective number of bits (enob) indicates the global accuracy of an adc at a specific input frequency and sampling rate. an ideal adcs error consists of quantiza - tion noise only. with an input range equal to the full-scale range of the adc, calculate the enob as follows: sinad - 1.76 enob 6.02 = total harmonic distortion total harmonic distortion (thd) is the ratio of the power contained in the first five harmonics of the converted data to the power of the fundamental. this is expressed as: 2345 1 pppp thd 10 log p ?? +++ = ?? ?? where p 1 is the fundamental power and p 2 through p 5 is the power of the 2nd- through 5th-order harmonics. spurious-free dynamic range spurious-free dynamic range (sfdr) is the ratio of the power of the fundamental (maximum signal component) to the power of the next-largest frequency component. aperture delay aperture delay (t ad ) is the time delay from the sampling clock edge to the instant when an actual sample is taken. aperture jitter aperture jitter (t aj ) is the sample-to-sample variation in aperture delay. full-power bandwidth a large -0.5dbfs analog input signal is applied to an adc, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by 3db. this point is defined as full-power input bandwidth frequency. maxim integrated 27 www.maximintegrated.com MAX11902 18-bit, 1msps, low-power, fully differential sar adc
+denotes lead(pb)-free/rohs-compliant package. *ep = exposed pad. *future productcontact factory for availability. part bits speed (ksps) fully differential input (max) (v) reference buffers package max11900* 16 1000 3.6 internal/external 4mm x 4mm tqfn-20 max11901 16 1600 3.6 internal/external 4mm x 4mm tqfn-20 MAX11902 18 1000 3.6 internal/external 4mm x 4mm tqfn-20 max11903 18 1600 3.6 internal/external 4mm x 4mm tqfn-20 max11904* 20 1000 3.6 internal/external 4mm x 4mm tqfn-20 max11905 20 1600 3.6 internal/external 4mm x 4mm tqfn-20 part temp range pin-package MAX11902etp+ -40c to +85c 20 tqfn-ep* package type package code outline no. land pattern no. 20 tqfn-ep t2044+5 21-0139 90-0429 maxim integrated 28 selector guide chip information process: cmos ordering information package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. www.maximintegrated.com MAX11902 18-bit, 1msps, low-power, fully differential sar adc
revision number revision date description pages changed 0 9/14 initial release ? 2014 maxim integrated products, inc. 29 revision history maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifcations without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. MAX11902 18-bit, 1msps, low-power, fully differential sar adc for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com.

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